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w wm8501 24-bit 192khz stereo dac with 1.7vrms line driver wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, july 2009, rev 4.2 copyright ? 2009 wolfson microelectronics plc description the wm8501 is a high performance stereo dac with an integrated 1.7vrms line driver. it is designed for audio applications that require a high voltage output along with enhanced load drive capability. the wm8501 supports data input word lengths from 16 to 24-bits and sampling rates up to 192khz. the wm8501 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo dac in a 14- lead soic package. the hardware control interface is used for the selection of audio data interface format, enable and de-emphasis. the wm8501 supports i 2 s, right justified or dsp interfaces. operating on separate analog and digital supplies the wm8501 offers very lower power consumption from the digital section, whilst supporting enhanced load drive from the analogue output. features ? stereo dac with 1.7vrms line driver from 5v analogue supply ? audio performance - 100db snr (?a? weighted @ 48khz) - -88db thd ? dac sampling frequency: 8khz ? 192khz ? pin selectable audio data interface format - i 2 s, 16-bit right justified or dsp ? 14-lead soic package ? 4.5v - 5.5v analogue, 2.7v - 5.5v digital supply operation applications ? stb ? dvd ? digital tv block diagram
wm8501 production data w pd, rev 4.2, july 2009 2 table of contents description ............................................................................................................1 features..................................................................................................................1 applications ..........................................................................................................1 block diagram ......................................................................................................1 table of contents ..............................................................................................2 pin configuration................................................................................................3 ordering information .......................................................................................3 pin description .....................................................................................................4 absolute maximum ratings..............................................................................5 recommended operating conditions ..........................................................5 electrical characteristics ...........................................................................6 master clock timing .................................................................................................. 7 digital audio interface ............................................................................................ 7 device description ..............................................................................................9 general introduction .............................................................................................. 9 dac circuit description ........................................................................................... 9 clocking schemes .....................................................................................................10 digital audio interface ...........................................................................................10 audio data sampling rates.....................................................................................12 hardware control modes .....................................................................................12 digital filter characteristics ....................................................................14 dac filter responses...............................................................................................14 digital de-emphasis characteristics ........................................................15 applications information ..............................................................................16 recommended external components .......................................................16 power up/down sequence......................................................................................17 recommended analogue low pass filter ........................................................17 pcb layout recommendations ..............................................................................18 package drawing...............................................................................................19 important notice ...............................................................................................20 address: ....................................................................................................................... .20
production data wm8501 w pd, rev 4.2, july 2009 3 pin configuration ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8501ged/v -40 to +85 o c 14-lead soic (pb-free) msl3 260c wm8501ged/rv -40 to +85 o c 14-lead soic (pb-free, tape and reel) msl3 260c note: reel quantity = 3,000
wm8501 production data w pd, rev 4.2, july 2009 4 pin description pin name type description 1 lrclk digital input sample rate clock input 2 din digital input serial audio data input 3 bclk digital input bit clock input 4 enable digital input enable input ? 0 = powered down, 1 = enabled 5 vmid analogue output analogue internal reference 6 rout analogue output right channel dac output 7 agnd supply ground reference for analog circuits and substrate connection 8 avdd supply positive supply for analog circuits 9 lout analogue output left channel dac output 10 dgnd digital supply digital ground supply 11 dvdd digital supply digital positive supply 12 deemph digital input de-emphasis select, internal pull down high = de-emphasis on low = de-emphasis off 13 format digital input data input format select, internal pull up low = 16-bit right justified or dsp (mode b) high = 16-24-bit i 2 s or dsp (mode a) 14 mclk digital input master clock input note: 1. digital input pins have schmitt trigger input buffers.
production data wm8501 w pd, rev 4.2, july 2009 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max analogue supply voltage -0.3v +7v digital supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v master clock frequency 38.462mhz operating temperature range, t a -40 c +85 c storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd 2.7 5.5 v analogue supply range avdd 4.5 5.5 v ground agnd, dgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v note: digital supply dvdd must never be more than 0.3v greater than avdd for normal operation of the device.
wm8501 production data w pd, rev 4.2, july 2009 6 electrical characteristics test conditions avdd = 5v, dvdd = 3.3v, gnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v output low v ol i ol = 2ma dgnd + 0.3v v output high v oh i oh = 2ma dvdd ? 0.3v v analogue reference levels reference voltage (vmid) avdd/2 v potential divider resistance r cap avdd to vmid and vmid to gnd 50 k dac output (load = 10k . 50pf) 0dbfs full scale output voltage at dac outputs 1.6 x avdd/5 1.7 x avdd/5 1.8 x avdd/5 vrms a-weighted, @ fs = 48khz 90 100 db a-weighted @ fs = 96khz 97 db signal to noise ratio (note 5,6,7) snr a-weighted @ fs = 192khz 97 db dynamic range (note 2, 6) dnr a-weighted, -60db full scale input 90 100 db total harmonic distortion (note 7) thd 1khz, load = 10k , 0dbfs -88 -78 db dac channel separation 93 db analogue output levels output level (line output) load = 10k , 0dbfs 1.7 vrms minimum resistance load (line output) to midrail or a.c. coupled 820 output level (headphone output) load = 16 , 0dbfs 1.0 vrms minimum resistance load (headphone output) to midrail or a.c. coupled 16 gain mismatch channel-to-channel 1 %fsr output d.c. level avdd/2 v supply current analogue supply current avdd = 5v 9 ma dvdd = 5v 8 ma digital supply current dvdd = 3.3v 4.5 ma power down current (note 4) avdd=dvdd=5v 0.01 ma notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured ?a? we ighted over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid pin decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). 4. power down occurs 1.5 s after mclk is stopped. 5. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results).
production data wm8501 w pd, rev 4.2, july 2009 7 6. dynamic range (db) ? dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd @ -60db= -32db, dr= 92db). 7. thd (db) ? thd is a ratio, of the rms values, of distortion/signal. 8. stop band attenuation (db) ? is the degree to which the frequency spectrum is attenuated (outside audio band). 9. channel separation (db) ? also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. master clock timing mclk t mclkl t mclkh t mclky figure 1 master clock timing requirements test conditions vdd = 5v, gnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information mclk master clock pulse width high t mclkh 8 ns mclk master clock pulse width low t mclkl 8 ns mclk master clock cycle time t mclky 20 ns mclk duty cycle 40:60 60:40 time from mclk stopping to power down. 1.5 12 s digital audio interface figure 2 digital audio data timing
wm8501 production data w pd, rev 4.2, july 2009 8 test conditions vdd = 5v, gnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bclk cycle time t bcy 40 ns bclk pulse width high t bch 16 ns bclk pulse width low t bcl 16 ns lrclk set-up time to bclk rising edge t lrsu 8 ns lrclk hold time from bclk rising edge t lrh 8 ns din set-up time to bclk rising edge t ds 8 ns din hold time from bclk rising edge t dh 8 ns
production data wm8501 w pd, rev 4.2, july 2009 9 device description general introduction the wm8501 is a high performance dac with an integrated 1.7vrms line driver from a 5v analogue supply, designed for digital consumer audio applications. the wm8501 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo dac and output smoothing filters. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. control of the internal functionality of the device is provided by hardware control pins (pin programmed). operation using master clocks of 256fs, 384fs, 512fs or 768fs is supported, selection between clock rates being automatically controlled. sample rates (fs) from less than 8khz to 96khz are allowed, provided the appropriate system clock is input. support is also provided for up to 192khz using a master clock of 128fs or 192fs. the audio data interface supports 16-bit right justified or 16-24-bit i 2 s (philips left justified, one bit delayed) interface formats. a dsp interface is also supported, enhancing the interface options for the user. split analog and digital 2.7-5.5v supply may be used, the output amplitude scaling with absolute analogue supply level. low supply voltage operation and low current consumption combined with the low pin count small package make the wm8501 attractive for many consumer applications. a power down mode is provided, allowing power consumption to be minimised. the device is packaged in a small 14-pin soic. dac circuit description the wm8501 dac is designed to allow playback of 24-bit pcm audio or similar data with high resolution and low noise and distortion. sample rates up to 192khz may be used, with much lower sample rates being acceptable provided that the ratio of sample rate (lrclk) to master clock (mclk) is maintained at one of the required rates. the two dacs on the wm8501 are implemented using sigma-delta oversampled conversion techniques. these require that the pcm samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the up to 192khz input rate. this sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor dac. the advantage of this technique is that the dac is linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical analogue components. a further advantage is that the high sample rate at the dac output means that smoothing filters on the output of the dac need only have fairly crude characteristics in order to remove the characteristic steps, or images on the output of the dac. to prevent the generation of unwanted tones dithering is used in the digital modulator along with a higher order modulator. the multi-bit switched capacitor technique used in the dac reduces sensitivity to clock jitter, and dramatically reduces out of band noise compared to switched current or single bit techniques. the voltage on the vmid pin is used as the reference for the dacs. therefore the amplitude of the signals at the dac outputs will scale with the amplitude of the voltage at the vmid pin. an external reference could be used to drive into the vmid pin if desired, with a value typically of about midrail ideal for optimum performance. the outputs of the 2 dacs are buffered out of the device by buffer amplifiers capable of driving into low impedance line loads as low as 820 or headphone loads down to 16 . the buffer amplifier output voltage level is set to 1.7v rms for line level loads when using a 5v analogue supply, avoiding the requirement for additional gain stages or higher voltage supplies in many applications. when driving headphone loads the output voltage level is limited to 1vrms. the advanced multi-bit dac used in wm8501 produces far less out of band noise than single bit traditional sigma delta dacs, and so in most applications where a line level output is required, no post dac filter is required. typically an ac coupling capacitor and a dc setting resistor to ground are the only components required on the output of the chip.
wm8501 production data w pd, rev 4.2, july 2009 10 clocking schemes in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. the external master clock can be applied directly through the mclk input pin with no configuration necessary for sample rate selection. note that on the wm8501, mclk is used to derive clocks for the dac path. the dac path consists of dac sampling clock, dac digital filter clock and dac digital audio interface timing. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the dac. the device can be powered down by stopping mclk. in this state the power consumption is substantially reduced. digital audio interface audio data is applied to the internal dac filters via the digital audio interface. three interface formats are supported: ? right justified mode ? i 2 s mode ? dsp mode all formats send the msb first. the data format is selected with the format pin. when format is low, right justified data format is selected and word lengths of 16-bits may be used. when the format pin is high, i 2 s format is selected and word length of any value up to 24-bits may be used. (if a word length shorter than 24-bits is used, the unused bits should be padded with zeros). if lrclk is 4 bclks or less duration, the dsp compatible format is selected. mode a and mode b clock formats are supported, selected by the state of the format pin. ?packed? mode (i.e. only 32 or 48 clo cks per lrclk period) operation is also supported in both i 2 s (16-24 bits) and right justified formats, (16 bit). if a ?packed? format of 16-bit word length is applied (16 bclks per lrclk half period), the device auto-detects this mode and switches to 16-bit data length. i 2 s mode the wm8501 supports word lengths of 16-24 bits in i 2 s mode. in i 2 s mode, the digital audio interface receives data on the din input. audio data is time multiplexed with lrclk indicating whether the left or right channel is present. lrclk is also used as a timing reference to indicate the beginning or end of the data words. in i 2 s modes, the minimum number of bclks per lrclk period is 2 times the selected word length. lrclk must be high for a minimum of word length bclks and low for a minimum of word length bclks. any mark to space ratio on lrclk is acceptable provided the above requirements are met. in i 2 s mode, the msb is sampled on the second rising edge of bclk following a lrclk transition. lrclk is low during the left samples and high during the right samples. figure 3 i 2 s mode timing diagram
production data wm8501 w pd, rev 4.2, july 2009 11 right justified mode the wm8501 supports word lengths of 16-bits in right justified mode. in right justified mode, the digital audio interface receives data on the din input. audio data is time multiplexed with lrclk indicating whether the left or right channel is present. lrclk is also used as a timing reference to indicate the beginning or end of the data words. in right justified mode, the minimum number of bclks per lrclk period is 2 times the selected word length. lrclk must be high for a minimum of word length bclks and low for a minimum of word length bclks. any mark to space ratio on lrclk is acceptable provided the above requirements are met. in right justified mode, the lsb is sampled on the rising edge of bclk preceding a lrclk transition. lrclk is high during the left samples and low during the right samples. figure 4 right justified mode timing diagram dsp mode a dsp compatible, time division multiplexed format is also supported by the wm8501. this format is of the type where a ?synch? pulse is followed by two data words (left and right) of predetermined word length. (16-bits). the ?synch? pulse replaces the normal duration lrclk, and dsp mode is auto-detected by the shorter than normal duration of the lrclk. if lrclk is of 4 bclk or less duration, the dsp compatible format is selected. mode a and mode b clock formats are supported, selected by the state of the format pin. figure 5 dsp mode a timing lrclk bclk din input w ord length (16 bits) 1/fs left channel 16 2 1 15 lsb msb 16 2 1 15 right channel no valid data 1 bclk 1 bclk max 4 bclk's
wm8501 production data w pd, rev 4.2, july 2009 12 figure 6 dsp mode b timing audio data sampling rates the master clock for wm8501 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (lrclk) typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. the wm8501 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 8 master clocks). if there is a greater than 8 clocks error, the interface shuts down the dac and mutes the output. the master clock should be synchronised with lrclk, although the wm8501 is tolerant of phase differences or jitter on this clock. master clock frequency (mhz) (mclk) sampling rate (lrclk) 128fs 192fs 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9344 22.5792 33.8688 48khz 6.144 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 1 master clock frequencies versus sampling rate hardware control modes the wm8501 is hardware programmable providing the user with options to select input audio data format, de-emphasis and mute. enable operation pin 4 (enable) controls the operation of the chip. if enable is low the device is held in a low power state. if this pin is held high the device is powered up. to ensure correct operation it is essential that there is a low to high transition on the enable pin after digital supplies have come on. this can be achieved by providing the enable signal from an external controller chip or by means of a simple rc network on the enable pin. see ?recommended external components? in the ?application information? section at the end of this datasheet. note that the enable pin should not be used as a mute pin or to temporarily silence the dac (between tracks of a cd for example). the enable pin is not intended to be used as a mute control but to allow entry into low power mode. disabling the device via the enable pin has the effect of powering down the voltage on the vmid pin. repeated enabling/disabling of the device can cause audible pops at the output. lrclk bclk din input word length (16 bits) 1/fs left channel 16 2 1 15 lsb msb 16 2 1 15 right channel no valid data 1 max 4 bclk's
production data wm8501 w pd, rev 4.2, july 2009 13 high performance mode on the rising edge of enable, the deemph pin is sampled. if it is low the device powers up normally. if it is high the device goes into a high performance and high power consumption state. once enable is high, deemph controls the selection of the de-emphasis filter. input audio format selection format (pin 13) controls the data input format. format input data mode 0 16 bit right justified 1 16?24 bit i 2 s table 2 input audio format selection notes: 1. in 16-24 bit i 2 s mode, any data from 16-24 bits or more is supported provided that lrclk is high for a minimum of data width bclks and low for a minimum of data width bclks, unless note 2. for data widths greater than 24 bits, the lsb?s will be truncated and the most significant 24 bits will be used by the internal processing. 2. if exactly 16 bclk cycles occur in both the low and high period of lrclk the wm8501 will assume the data is 16-bit and accept the data accordingly. input dsp format selection format 50% lrclk duty cycle lrclk of 4 bclk or less duration 0 16 bit (msb-first, right justified) dsp format ?mode b 1 i 2 s format up to 24 bit (philips serial data protocol) dsp format ?mode a table 3 dsp interface formats de-emphasis control deemph (pin 12) is an input control for selection of de-emphasis filtering to be applied. deemph de-emphasis 0 off 1 on table 4 de-emphasis control
wm8501 production data w pd, rev 4.2, july 2009 14 digital filter characteristics parameter symbol test conditions min typ max unit passband edge -3db 0.487fs passband ripple f < 0.444fs 0.05 db stopband attenuation f > 0.555fs -60 db table 5 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 7 dac digital filter frequency response - 44.1, 48 and 96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 8 dac digital filter ripple - 44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 9 dac digital filter frequency response - 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 10 dac digital filter ripple - 192khz
production data wm8501 w pd, rev 4.2, july 2009 15 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 11 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 12 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 13 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 14 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 15 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 16 de-emphasis error (48khz)
wm8501 production data w pd, rev 4.2, july 2009 16 applications information recommended external components figure 17 external component diagram in an application where enable is fed directly from vdd rather than a dedicated control line, resistor r3 and capacitor c9 are used on the enable pin to introduce a short delay in the low to high transition of enable. this will ensure the pin goes high after power supplies have had time to settle (see ?enable operation? in the ?hardware control modes? section of the datasheet). however, if the enable signal is being provided from an external controller chip rather than vdd directly, r3 and c9 will not be required.
production data wm8501 w pd, rev 4.2, july 2009 17 power up/down sequence power up/down sequence for click free operation, the wm8501 should be powered up and down in a specific sequence. power-up: 1. power up avdd and dvdd and wait to settle 2. turn on clocks and data (mclk, bclk, lrclk, sdata) 3. switch enable pin from low to high power-down: 1. switch enable from high to low 2. remove clocks and data 3. power down avdd and dvdd recommended analogue low pass filter figure 18 recommended 1 st order low pass filter note: capacitors should be cog dielectric. an external single pole rc filter is recommended (see figure 18) if the device is driving a wideband amplifier. however the wm8501 does contain an internal low pass filter which should be adequate in most applications.
wm8501 production data w pd, rev 4.2, july 2009 18 pcb layout recommendations care should be taken in the layout of the pcb that the wm8501 is to be mounted to. the following notes will help in this respect: 1. the vdd supply to the device should be as noise free as possible. this can be accomplished to a large degree with a 10uf bulk capacitor placed locally to the device and a 0.1uf high frequency decoupling capacitor placed as close to the vdd pin as possible. it is best to place the 0.1uf capacitor directly between the vdd and gnd pins of the device on the same layer to minimize track inductance and thus improve device decoupling effectiveness. 2. the vmid pin should be as noise free as possible. this pin provides the decoupling for the on chip reference circuits and thus any noise present on this pin will be directly coupled to the device outputs. in a similar manner to the vdd decoupling described above, this pin should be decoupled with a 10uf bulk capacitor local to the device and a 0.1uf capacitor as close to the vmid pin as possible. 3. separate analogue and digital track routing from each other . the device is split into analogue (pins 5 ? 9) and digital (pins 1 ? 4 and pins 10 ? 14) sections that allow the routing of these signals to be easily separated. by physically separating analogue and digital signals, crosstalk from the pcb can be minimized. 4. use an unbroken solid gnd plane . to achieve best performance from the device, it is advisable to have either a gnd plane layer on a multilayer pcb or to dedicate one side of a 2 layer pcb to be a gnd plane. for double sided implementations it is best to route as many signals as possible on the device mounted side of the board, with the opposite side acting as a gnd plane. the use of a gnd plane greatly reduces any electrical emissions from the pcb and minimizes crosstalk between signals. further advice on this subject is available in wan0129, available from www.wolfsonmicro.com
production data wm8501 w pd, rev 4.2, july 2009 19 package drawing notes: a. all linear dimensions are in millimeters (inches). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm (0.010in). d. meets jedec.95 ms-012, variation = ab. refer to this specification for further details. symbols dimensions (mm) dimensions (inches) min max min max a 1.35 1.75 0.0532 0.0688 a1 0.10 0.25 0.0040 0.0098 b 0.33 0.51 0.0130 0.0200 c 0.19 0.25 0.0075 0.0098 d 8.55 8.75 0.3367 0.3444 e 3.80 4.00 0.1497 0.1574 e 1.27 bsc 0.05 bsc h 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.0099 0.0196 l 0.40 1.27 0.0160 0.0500 0 o 8 o 0 o 8 o ref: jedec.95, ms-012 0.10 (0.004) seating plane dm001.c e d: 14 pin soic 3.9mm wide body h b d a a1 c h x 45 o -c- 8 7 1 14 l e
wm8501 production data w pd, rev 4.2, july 2009 20 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the righ t to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectua l property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective thir d party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed the reon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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